This study presents the design and implementation of the Ascon lightweight hash function, compliant with the NIST standard, on FPGA for Internet of Things (IoT) applications. The hash function is specifically designed to reduce energy consumption and enhance performance in resource-constrained environments, utilizing optimization algorithms to minimize hardware complexity. Simulation and implementation results demonstrate that the proposed design outperforms existing methods in terms of speed, power consumption, and hardware resource utilization, making it an ideal solution for security applications in IoT. Research Aim: The aim of this study is to design and implement a lightweight hash function based on the NIST standard on FPGA to meet the security requirements of the Internet of Things (IoT). The Ascon algorithm is identified as an optimal candidate for this implementation. The hash function is designed to minimize power consumption and hardware footprint while ensuring sufficient performance and security for resource-constrained IoT environments. This design enables the provision of optimized and scalable solutions for securing data in small, widely used IoT devices. Research method: This research involves several main steps. First, the security requirements and hardware/software constraints associated with the Internet of Things (IoT) are analyzed. Subsequently, a lightweight hashing algorithm based on the NIST standard is selected and optimized for FPGA implementation, with the Ascon algorithm chosen for this thesis. The hardware design of the algorithm is carried out using hardware description languages such as VHDL, and simulation and synthesis tools are employed to evaluate its performance, power consumption, and resource utilization. Finally, the design is implemented on a real FPGA platform, and its efficiency in terms of speed, power consumption, and hardware resource usage is assessed and compared with existing approaches. Findings: The VHDL implementation demonstrates that the designed hash function can process data at high speeds, making it ideal for real-time IoT applications. The design is optimized to minimize the use of FPGA hardware resources, including gates, lookup tables (LUTs), and memory blocks, enabling deployment on small and cost-effective FPGAs. Furthermore, the VHDL implementation shows that the design is highly adaptable to various FPGA architectures and can be customized for a wide range of IoT applications.

: Hash Functions, Lightweight, FPGA, NIST, IoT Applications