As technology develops, semiconductors' sizes and separations are getting smaller by the day. Therefore, as the fundamental charge of the fragile nodes drops, SRAM cells used in aerospace applications are more vulnerable to soft-error. If a radiation particle strikes a sensitive node in a standard 6T SRAM cell, single-event upsets (SEUs) might result in data inversion. This research suggests a Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T (SARP12T) SRAM cell to mitigate the effects of SEUs. The performance of SARP12T is compared to that of other recently introduced soft-error-aware SRAM cells, including RHD12T, RHPD12T, QUCCE12T, QUATRO12T, and RSP14T. The data could be retrieved even if a radiation assault flips the values of the vulnerable nodes in SARP12T. SARP12T can withstand single-event multi-node upsets (SEMNUs) caused by storage node pairs. During read operation, the bitline provides easy access to the '0' storing memory nodes in the proposed cell, which are also very resilient to disruptions. In terms of energy usage, SARP12T is likewise the most effective holding technique. When it comes to write performance, SARP12T performs better than rival cells, and its write latency is significantly shorter. All of these benefits are obtained by the proposed cell with just a little increase in read/write energy and read latency.

Aerospace, SARP12T, QUCCE12T, SRAM