The boom of high speed recent communication hardly requires the efficient Mathematical operations. The favored performance outcomes of any architecture are possible only by the effective Mathematical operations. Squaring plays an essential role in high speed applications like animation, Digital signal processing, and image processing, etc. where the speed is a crucial performance characteristic. The squaring operation involves more computing time; hence the speed of the squaring operation has to be improved. This paper explains about the proposed squaring architecture using Yavadunam which is one of the sutras of the ancient Indian Vedic Mathematics. The deficiency is obtained from Yavadunam thereby reducing the deficiency bit size to N-1 bits. Here the bit size is constantly sustained to N-1 bits. Thereby N*N bit multiplier is replaced by N-1*N-1. The proposed architecture results in reduced usage of components with reduction in critical path delay and increased speed.

Squaring, Vedic Mathematics, Yavadunam Sutra, Bit reduction