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Research Article | Open Access
Volume 13 2021 | None
LOW-POWER, AREA-OPTIMIZED 4-BIT SEQUENCE DIGITAL COUNTER: DESIGN AND PERFORMANCE ANALYSIS
SHIVAPRASAD MARTHA, KOTESWARA RAO GANNA, VEDAVATHI GONELA, DIVELLA RASHMITHA, FAAMIYA AAFREEN
Pages: 3763-3771
Abstract
The low power VLSI circuit aims to improve battery life and performance while reducing the system's power consumption and energy footprint. The scaling architecture, also referred to as a counter, alters an operator's values based on its prior state. Data about time and frequency may be obtained from the counting process. The main cause of scaling circuits' high power consumption is clock power dissipation during standby. The clock signal consumes around one-third of a counter's total power. This research reduces the number of switches utilised to conserve energy. The counter's low power consumption is the outcome of efforts to lessen the strain on the flip-flops. To achieve this, SVL (Self-Controllable Voltage Level) in conjunction with TSPCL is a good choice. The Flip-Flop operation may be carried very quickly and with less power consumption using TSPCL. Because it uses fewer transistors and hence uses less energy because of leakage current, the SVL approach is easier to understand. Compared to the old model, the new one uses 27% less energy. The suggested approach finds practical uses for state-of-the-art, low-power technologies.
Keywords
flip-flops, SVL, and TSPCL.
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