SRAM is developed for memory interface in digital system design. Data stored in SRAM are vulnerable to error due to hardware or software error. Secrete Unknown Ciphers (SUC) is proposed as a mean of provisioning of security in data storage. In digital system design digital clone-resistant functions were developed in overcoming the issues with Physical(ly) Unclonable Functions (PUF). However the desiring has a issue with the synchronization mean for security provisioning. The recent developed approach SRAM-SUC is developed using block cipher coding. However, the latency due to delay metric in the design process limits its application. In this paper, a new synchronous approach for SRAM-SUC design is proposed using delay monitoring parameter in latency controlling. The proposed approach illustrated a higher power saving using different FPGA devices

SRAM-SUC, PUF, security coding, resource optimization, block coding.