Deep Learning, a part of Artificial Intelligence, uses deep neural networks. These networks need a lot of resources and efficient design to work well. They also require high memory and parallel processing. Building these networks is tough because they need large components like MAC units and activation functions. Edge-AI applications need high-speed accelerators, which use more space and power. To make a good DNN accelerator without losing much speed, we need to improve MAC design, activation functions, and network complexity. ASIC-based hardware designs for DNNs have limited space and flexibility. This study looks at creating low-power and efficient DNN accelerators using the CORDIC architecture for MAC and activation functions. CORDIC designs are efficient but slow. To fix this, we suggest a pipelined architecture for CORDIC-based MAC and activation functions. Pipelining uses more resources, so we study the balance between stages and accuracy to get high speed. We offer different designs for CORDIC-based MAC and activation functions with iterative and pipelined approaches. he proposed design’s system parameters and hardware can be adjusted for specific applications. Iterative architecture is good for AI-enabled IoT applications with minimal speed loss. Pipeline architecture is better for Edge-AI, offering high speed but using more space and power. We developed a digital solution to design and implement a deep neural network for ASIC and FPGA platforms. DNNs work well with both digital and analog inputs. An ADC is needed to convert analog input to digital for processing. This study also focuses on designing a low-power, high-speed 4-bit Flash ADC to handle both analog and digital inputs. The ADC works effectively at a sampling rate of 2.4 GS/s and is used in analog-digital interface accelerators. Overall, the proposed designs use fewer hardware resources and less power, which is important for edge computing solutions.

Multiply-and-Accumulate, activation function, Co-ordinate Rotation Digital Computer,