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Research Article | Open Access
Volume 13 2021 | None
OPTIMIZED VLSI DESIGN FOR CONVOLUTIVE BLIND SOURCE SEPARATION APPLICATIONS
GANESH URUGONDA, VEERAMALLA SUMALINI, RANGAREE HIVRAJ PANKAJ, CHERUKUPELLI SUPRIYA, CHIRRA SINDHU
Pages: 3813-3817
Abstract
A basic signal processing method utilised in many fields, such as image, audio, and biological signal processing, is blind source separation (BSS). Convolutive BSS is a particularly difficult problem since it aims to separate mixed sources while the mixing process is described by convolution. In order to satisfy the requirements of real-time and effective processing in applications including echo cancellation, audio source separation, and speech enhancement, this study presents a unique VLSI (Very Large Scale Integration) architecture designed for convolutive blind source separation. The suggested VLSI architecture achieves complicated BSS with low latency and high accuracy by utilising cutting-edge hardware innovations and algorithms. It combines many processing components, each of which is in charge of locating and isolating the distinct source signals from the mixture being monitored. These processing components improve separation performance even when dealing with time-varying mixture circumstances by iteratively refining source estimations using advanced signal processing and adaptive filtering approaches. Memory-efficient data structures, adaptive parameter tuning, and parallel processing units are crucial elements of the VLSI architecture. Because it can handle varying input volumes and adapt to various processing needs, it is appropriate for a variety of real-world applications. The experimental findings show that the suggested VLSI design is efficient and effective in convolutive BSS conditions. It also shows that it can separate mixed sources in real time with high-quality signals. The hardware architecture is a useful tool for signal processing systems that must extract significant source information from complicated mixes because to its scalability and durability.
Keywords
high efficiency, memory, VLSI, and BSS.
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